The present invention generally relates to power detectors for use in wireless communication systems, and relates in particular to systems and method for reducing power consumption and improving power control of a wireless communication system.
Wireless communication systems generally include transmitter and receiver circuits that have power (e.g., current) requirements that vary during use, due at least in part, to usage, network characteristics, and antenna characteristics. For example, the power required for signal transmission through an antenna may vary, and it is generally important to monitor the output power of the transmitter during use. Failure to monitor this output power may result in too little power being employed, which may lead to dropped calls, or may result in too much power being used, which may lead to decreased useful battery life and/or network jamming.
For example, U.S. Pat. No. 6,265,939 discloses a power detector that employs a rectifying diode circuit that senses a peak RF signal coupled thereto, and the circuit provides a linear power detection functionality.
U.S. Pat. No. 7,353,006 disclose systems and methods for detecting output power in a transmission system that includes a power amplifier, a track and hold circuit, a log power detector in a feedback path, and a log power detector in a reference path in communication with the track and hold circuit. Such systems provide a wider range of detection of a logarithmic scale, but operate continuously and consume an amount of current that is not insubstantial, at least in part, due to the fact that such systems employ the use of logarithmic amplifiers in the power detection circuits.
Battery power requirements of wireless transmission systems that employ power amplifiers typically require that current use be minimized. U.S. Pat. No. 6,756,849 discloses power detector systems for CMOS devices that employ a first envelope detector that is coupled to a voltage sensor, and a second envelope detector that is coupled to a current sensor. Although the system is disclosed to be suitable for use with CMOS systems that employ dual gate oxide devices for using two power levels, the envelope detectors are disclosed to be logarithmic amplifiers in accordance with an embodiment, and the system operates continuously.
It is also known that transmission circuits and coupling interfaces present a certain amount of impedance and reflected power, and that it is generally desirable to reduce any varying mismatches in load impedance that may occur during use. U.S. Pat. No. 5,564,086 discloses a system that includes a variable matching network, a directional coupler, and a processor that digitizes the forward and reflected components, and provides a feedback control signal to the variable matching network. U.S. Patent Application Publication No. 2005/0059362 discloses a power amplifier that internally corrects for any load mismatch without the use of a separate variable matching network, but instead provides mismatch protection within the power amplifier itself, which requires additional circuitry in the power amplifier.
There is a need, therefore, for a system and method for providing power detection with reduced current requirements, and in particular a need for providing a system and method for detecting forward and reflected power in a transmission system, and for determining the magnitude of impedance mismatch in a transmission system in a wireless communication system.